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256 Kilobit (32K x 8) SuperFlash MTP
SST27SF256, SST27VF256
Preliminary Specifications
FEATURES: * 5.0-Volt Read Operation for 27SF256 * * 2.7-Volt Read Operation for 27VF256 Superior Reliability - Endurance: Minimum 1000 Cycles - Greater than 100 years Data Retention Low Power Consumption: - Active Current: 20 mA (typical) for 5V and 10mA (typical) for 2.7V - Standby Current: 10 A (typical) for both 27SF256 and 27VF256 Fast Access Time: - 5.0-Volt Read - 55 and 70 - 2.7-Volt Read - 120 and 150 ns
*
* Fast Programming Operation - 20 s per byte (guaranteed) - 0.8 second for the entire chip * Features Electrical Erase: - Does Not Require UV Source - Chip Erase Time: 100 ms * TTL I/O Compatibility * JEDEC Standard Byte-wide EPROM Pinouts * 12V Power Supply for Programming/Erase * Packages Available - 32-Pin PLCC - 28 Pin Plastic DIP - 28 Pin TSOP
1 2 3 4 5 6
*
PRODUCT DESCRIPTION The 27SF256/27VF256 are 32K x 8 CMOS, many-time programmable (MTP) low cost flash, manufactured with SST's proprietary, high performance SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The 27SF256/ 27VF256 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The 27SF256/27VF256 have to be erased prior to programming. The 27SF256/27VF256 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance byte programming, the 27SF256/27VF256 provide a byte-program time of 20 s. The entire memory can be programmed byte by byte in less than 0.8 seconds. Designed, manufactured, and tested for a wide spectrum of applications, the 27SF256/ 27VF256 are offered with an endurance of 1000 cycles. Data retention is rated at greater than 100 years. The 27SF256/27VF256 are suited for applications that require infrequent rewrites and low power nonvolatile storage. The 27SF256/27VF256 will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UVEPROMs, OTPs, and mask ROMs.
To meet surface mount and conventional through hole requirements, the 27SF256/27VF256 are offered in 32-pin PLCC, 28-pin PDIP and 28-pin TSOP packages. See Figures 1 and 2 for pinouts. Device Operation The 27SF256/27VF256 are low cost flash solutions that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. They are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, the device also supports Electrical Erase operation. The 27SF256/27VF256 do not require a UV source to erase, and therefore the packages do not have a window. Read The Read operation of the 27SF256/27VF256 are controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE - TOE. The VPP pin must be VCC or VSS during read operation. When the CE# pin is high, the chip is deselected and a typical standby current of 10 A is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
7 8 9 10 11 12 13 14 15 16
(c) 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon storage Technology, Inc. 1 321-04 11/97 These specifications are subject to change without notice.
256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications Programming operation The 27SF256/27VF256 are usually programmed by using an external programmer. The programming mode is activated by asserting 12V (5%) on Vpp pin, Vcc = 5V5%, VIL on CE# pin, and VIH on OE# pin. The device is programmed byte by byte with the desired data at the desired address using a single pulse (CE# pin low) of 20 s. Using the SuperFlash programming algorithm, the byte programming process continues byte by byte until the entire chip (32 Kbytes) has been programmed. Chip Erase Operation The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". Unlike traditional EPROMs, which use UV light to do the chip erase, the 27SF256/27VF256 use an electrical chip erase operation. This saves a significant amount of time (about 30 minutes for each erase operation, compared with UV erase). The entire chip can be erased in 100 ms (CE# pulse). In order to activate the erase mode, the 12V (5%) is applied to VPP and A9 pins, Vcc = 5V5%, VIL on CE# pin, and VIH on OE# pin. All other address and data pins are "don't care". The falling edge of CE# will start the Chip Erase operation. Once the chip has been erased, all bytes must be verified for FF. Refer to figure 8 for the flow chart. The 27SF256/27VF256 can also be reprogrammed in the system. This requires the availability of 12V for VPP to program and an additional 12V for address A9 to erase. Product Identification Mode The product identification mode identifies the device as the 27SF256 or 27VF256 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force VH (12V5%) on address A9 with VPP pin at 5V10%. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation.
TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 H 27SF256 Device Code 0001 H 27VF256 Device Code 0001 H
Data BF H A3 H C3 H
321 PGM T1.0
FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF256/27VF256
X-Decoder
262,144 Bit EEPROM Cell Array
A14 - A0
Address Buffer Y-Decoder
CE# OE# VPP A9
Control Logic
I/O Buffers
DQ7 - DQ0
321 MSW B1.0
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications
OE# A11 A9 A8 A13 A14 VCC VPP A12 A7 A6 A5 A4 A3
22 23 24 25 26 27 28 1 2 3 4 5 6 7
Standard Pinout Top View Die up
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2
321 MSW F01.0
1 2 3 4 5
FIGURE 1: PIN ASSIGNMENTS FOR 28-PIN TSOP PACKAGES
A12 A7 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 VCC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 DQ1 DQ2 VSS A6 A5 A4 A3 A2 A1 A0 NC DQ0 5 6 7 8 9 10 11 12 13 14 15 16 VPP 3 2
NC VCC 1
A14 A13
6
29 28 27 A8 A9 A11 NC OE# A10 CE# DQ7 DQ6
4
32 31 30
7 8 9 10
321 MSW F02.1
28-Pin PDIP
23 22
32-Lead PLCC Top View
26 25 24 23 22 21
21 Top View 20 19 18 17 16 15
17 18 19
20
DQ3 DQ5 NC DQ4
FIGURE 2: PIN ASSIGNMENTS FOR 28-PIN PLASTIC DIPS AND 32-LEAD PLCCS TABLE 2: PIN DESCRIPTION Symbol Pin Name A14-A0 Address Inputs DQ7-DQ0 Data Input/Output CE# OE# VCC VPP VSS NC Chip Enable Output Enable Power Supply Power Supply for Program or Erase Ground No Connection
11 12 13 14 15 16
Functions To provide memory addresses To output data during read cycles and receive input data during program cycle, the outputs are in tri-state when OE# or CE# is high To activate the device when CE# is low To gate the data output buffers during read operation and high voltage pin during chip erase and programming operation To provide 5-volt supply (10%) for the 27SF256 and 3-volt supply (2.7-3.6 V) for the 27VF256 High voltage pin during chip erase and programming operation 12-volt (5%) Unconnected pins
321 PGM T2.0
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications TABLE 3: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Output Disable Program Standby Chip Erase Program/Erase Inhibit Product Identification
Note:
VIL VIL VIH VIL VIH VIL
VIH VIH X VIH X VIL
VPP VCC or VSS VCC or VSS VPPH VCC or VSS VPPH VPPH VCC or VSS
A9 AIN X AIN X VH X VH
DQ DOUT High Z DIN High Z High Z High Z Manufacturer Code (BF) Device Code (A3 for 27SF256 & C3 for 27VF256)
Address AIN X AIN X X X A14-A1 = VIL, A0 = VIL A14-A1 = VIL, A0 = VIH
321 PGM T3.0
X = VIL or VIH VPPH = 12V5%, VH = 12V5%
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential .............................................................................. -0.5V to VCC+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .......................................................... -1.0V to VCC+1.0V Voltage on A9 and Vpp Pin to Ground Potential .................................................................................. -0.5V to 14.0V Package Power Dissipation Capability (TA = 25C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ............................................................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
27SF256 OPERATING RANGE Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C
AC CONDITIONS OF TEST VCC 5V10% 5V10% Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF See Figures 6 and 7
27VF256 OPERATING RANGE Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C
AC CONDITIONS OF TEST VCC 2.7-3.6V 2.7-3.6V Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF See Figures 6 and 7
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications TABLE 4: 27SF256 READ MODE DC OPERATING CHARACTERISTICS Vcc = 5 V10%, TA = 0C to 70C (Commercial) or -40C to +85C (Industrial) Limits Symbol Parameter Min Max Units Test Conditions ICC VCC Read Current 30 mA CE# = OE# = VIL all I/Os open, Address input = VIL/VIH at f = 1/TRC Min., VCC = VCC Max IPPR VPP Read Current 100 A CE# = OE# = VIL, all I/Os open, Address input = VIL/VIH at f = 1/TRC Min., VCC = VCC Max ,Vpp = Vcc ISB1 Standby VCC Current 3 mA CE# = OE# = VIH, VCC = VCC Max. (TTL input) ISB2 Standby VCC Current 50 A CE#=OE#=VCC-0.3V. (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 A VIN = GND to VCC, VCC = VCC Max. ILO Output Leakage Current 10 A VOUT = GND to VCC, VCC = VCC Max. VIL Input Low Voltage 0.8 V VCC = VCC Max. VIH Input High Voltage 2.0 Vcc+0.5 V VCC = VCC Max. VOL Output Low Voltage 0.4 V IOL = 2.1 mA, VCC = VCC Min. VOH Output High Voltage 2.4 V IOH = -400 A, VCC = VCC Min. IH Supervoltage Current 100 A CE# = OE# = VIL, A9 = VH Max. for A9
321 PGM T4.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TABLE 5: 27VF256 READ MODE DC OPERATING CHARACTERISTICS Vcc = 2.7-3.6V, TA = 0C to 70C (Commercial) or -40C to +85C (Industrial) Limits Symbol Parameter Min Max Units Test Conditions ICC Vcc Read Current 12 mA CE#=OE#=VIL all I/Os open, Address input = VIL/VIH at f=1/TRC Min., VCC=VCC Max IPPR VPP Read Current 100 A CE# = OE# = VIL, all I/Os open, Address Input = VIL/VIH at f = 1/TRC Min, VCC = VCC Max, Vpp = Vcc ISB1 Standby VCC Current 1 mA CE#=OE#=VIH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 15 A CE#=OE#=VCC -0.3V. (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 A VIN =GND to VCC, VCC = VCC Max. ILO Output Leakage Current 10 A VOUT =GND to VCC, VCC = VCC Max. VIL Input Low Voltage 0.8 V VCC = VCC Max. VIH Input High Voltage 2.0 Vcc+0.5 V VCC = VCC Max. VOL Output Low Voltage 0.4 V IOL = 100 A, VCC = VCC Min. VOH Output High Voltage 2.4 V IOH = -100 A, VCC = VCC Min. IH Supervoltage Current 100 A CE# = OE# = VIL, A9 = VH Max. for A9
321 PGM T5.2
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications TABLE 6: 27SF256/27VF256 PROGRAM/ERASE DC OPERATING CHARACTERISTICS Vcc = 5 V10%, Vpp = VPPH,TA = 25C5C Limits Symbol Parameter Min Max Units Test Conditions ICP VCC Erase or Program 30 mA CE# = VIL, Vpp = 12V5%, VCC = VCC Max Current IPP VPP Erase or Program 1 mA CE# = VIL, Vpp = 12V5%, VCC = VCC Max Current ILI Input Leakage Current 1 A VIN = GND to VCC, VCC = VCC Max ILO Output Leakage Current 10 A VOUT = GND to VCC, VCC = VCC Max VH Supervoltage for A9 11.4 12.6 V CE# = OE# = VIL IH Supervoltage Current 100 A CE# = OE# = VIL, A9 = VH Max for A9 VPPH High Voltage for VPP Pin 11.4 12.6 V
321 PGM T6.1
TABLE 7: POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up to Read Operation
Maximum 100
Units s
321 PGM T7.0
TABLE 8: CAPACITANCE (TA = 25 C, f=1 MHz, other pins open) Parameter Description Test Condition (1) CI/O I/O Pin Capacitance VI/O = 0V CIN(1) Input Capacitance VIN = 0V
Maximum 12 pF 6 pF
321 PGM T8.0
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention (1) VZAP_HBM ESD Susceptibility Human Body Model (1) VZAP_MM ESD Susceptibility Machine Model (1) ILTH Latch Up
Note:
(1)
Minimum Specification 1000 100 2000 300 100
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
321 PGM T9.1
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications AC CHARACTERISTICS TABLE 10: 27SF256 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 27SF256-55 Min Max 55 55 55 25 0 0 20 20 0 27SF256-70 Min Max 70 70 70 30 0 0 25 25 0 Units ns ns ns ns ns ns ns ns ns
321 PGM T10.1
1 2 3 4 5 6 7
Units ns ns ns ns ns ns ns ns ns
321 PGM T11.0
TABLE 11: 27VF256 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 27VF256-120 Min Max 120 120 120 50 0 0 30 30 0 27VF256-150 Min Max 150 150 150 60 0 0 30 30 0
8 9 10 11 12 13 14 15 16
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications TABLE 12: PROGRAMMING/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min TPRT VPP Pulse Rise Time 50 TAS Address Setup Time 2 TAH Address Hold Time 2 TVPS VPP Setup Time 2 TVPH VPP Hold Time 2 TPW CE# Program Pulse Width 20 TEW CE# Erase Pulse Width 100 TDS Data Setup Time 2 TDH Data Hold Time 2 TVR VPP and A9 Recovery Time 2 TART A9 Rise Time to 12V during Erase 50 TAPS A9 Setup Time during Erase 2 TAPH A9 Hold Time during Erase 2 Max Units ns s s s s s ms s s s ns s s
321 PGM T12.1
40 500
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications
TRC ADDRESS
TAA
1 2
CE#
TCE
OE#
TOE TOLZ TOH
DATA VALID
3
TOHZ TCHZ
DATA VALID
DQ7-0
HIGH-Z
4 5
321 MSW F03.0
TCLZ VCC Vpp VSS
6 7
FIGURE 3: READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT A9) CE# TEW OE# VIH
8 9 10 11
DQ7-0 VPPH VCC Vpp VSS VPPH A9 VIH VIL TART TA9H TA9S TVR TPRT TVPS TVPH TVR
12 13 14 15 16
321 MSW F04.0
FIGURE 4: ERASE TIMING DIAGRAM
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications
ADDRESS
ADDRESS VALID
TAS CE#
TAH
TPW OE# VIH TDS TDH
DQ7-0
HIGH-Z
DATA VALID
VPPH VCC Vpp VSS TPRT TVPH TVPS
TVR
321 MSW F05.0
FIGURE 5: PROGRAM TIMING DIAGRAM
2.4 INPUT
2.0 REFERENCE POINTS 0.8
2.0 OUTPUT 0.8
0.4
321 MSW F06.0
AC test inputs are driven at VOH (2.4 VTTL) for a logic "1" and VOL (0.4 VTTL) for a logic "0". Measurement reference points for inputs and outputs are VIH (2.0 VTTL) and VIL (0.8 VTTL). Inputs rise and fall times (10% 90%) are <10 ns. FIGURE 6: AC INPUT/OUTPUT REFERENCE WAVEFORMS
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications
TEST LOAD EXAMPLE
VCC
TO TESTER
1 2
RL HIGH
3
TO DUT
4
CL RL LOW
5 6
321 MSW F07.0
7 8 9 10 11 12 13 14 15 16
FIGURE 7: TEST LOAD EXAMPLE
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications
Start
VPP = VPPH , A9 = VH
Erase 100 ms pulse (CE# = VIL)
VPP = VCC or VSS A9 = VIL or VIH
Wait for VPP and A9 Recovery Time
Device into Read Mode (CE# = OE# = VIL)
No Compare All bytes to FF Yes Device Failed
Device Passed
321 MSW F08.0
FIGURE 8: ERASE ALGORITHM
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications
Start
1
See Figure 8
Erase
2
VPP = VPPH
3
Address = First Location
4
Program 20 s pulse (CE# = VIL)
5 6
Increment Address No
Last Address? Yes
VPP = VCC or VSS
7
Wait for VPP Recovery Time Device into Read mode (CE# = OE# = VIL)
8 9
Compare All bytes to original data Yes Device Passed
No
10
Device Failed
321 MSW F09.0
11 12 13 14 15 16
FIGURE 9: PROGRAMMING ALGORITHM
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications PRODUCT ORDERING INFORMATION
Device SST27XF256
Speed - XXX -
Suffix1 XX -
Suffix2 XX Package Modifier H = 32 leads, G = 28 leads Numeric = Die modifier Package Type P = PDIP N = PLCC K = TSOP (die up) U = Unencapsulated die Operating Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 3 = 1000 cycles Read Access Speed 55 = 55 ns, 70 = 70 ns, 120 = 120 ns, 150 = 150 ns Read Voltage S = 5.0 Volt Read V = 2.7 Volt Read (2.7-3.6V)
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications 27SF256 Valid combinations SST27SF256- 55-3C-KG SST27SF256- 55-3C-NH SST27SF256- 70-3C-KG SST27SF256- 70-3C-NH SST27SF256- 55-3I-KG SST27SF256- 70-3I-KG SST27SF256- 55-3I-NH SST27SF256- 70-3I-NH SST27SF256- 55-3C-PG SST27SF256- 70-3C-PG
1 2 3 4
SST27SF256- 70-3C-U1
27VF256 Valid combinations SST27VF256- 120-3C-KG SST27VF256- 120-3C-NH SST27VF256- 150-3C-KG SST27VF256- 150-3C-NH SST27VF256- 120-3I-KG SST27VF256- 150-3I-KG SST27VF256- 120-3I-NH SST27VF256- 150-3I-NH
SST27VF256- 120-3C-PG SST27VF256- 150-3C-PG
SST27VF256-150-3C-U1
5 6 7 8 9 10 11 12 13 14 15 16
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications PACKAGING DIAGRAMS
Note: 1. Complies with JEDEC publication 95 MO-183 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (.05) mm.
28pn TSOP KG AC.3
28-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: KG
Note: 1. Complies with JEDEC publication 95 MO-015 AH dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
28pn PDIP PG AC.2
28-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PG
(c) 1998 Silicon Storage Technology, Inc.
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256 Kilobit SuperFlash MTP SST27SF256, SST27VF256
Preliminary Specifications
1 2 3 4 5 6
32pn PLCC NH AC.3 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
7 8 9 10 11 12 13 14 15 16
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
(c) 1998 Silicon Storage Technology, Inc.
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